Keynote speeches:


Juan C. Rey, Mentor, a Siemens business

EDA and semiconductor industries perspectives


Juan C. Rey, vice president of Engineering, Calibre, joined Mentor in 2001 as senior engineering director for Mentor’s industry-leading Calibre product line, directing all development activities for Calibre products. Previously he was vice-president of Engineering at Exend Corporation, managing all software development and quality activities. Prior to that he was engineering director for Physical Verification at Cadence Design Systems. Earlier positions include: manager/developer for Process Modeling and Parasitic Extraction at Technology Modeling Associates; visiting scholar/science and engineering associate at Stanford University; senior research engineer at INVAP, Argentina; and associate professor at Universidad Nacional del Comahue, Argentina. Juan holds a degree in Nuclear Engineering from Universidad Nacional de Cuyo, Argentina. The author or co-author of numerous papers and conference presentations, he serves on the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC) and the UCLA Center for Domain-Specific Computing.


Prof. Paul S. Ho, The University of Texas at Austin

Effects of Scaling and Stress on Electromigration of Nanointerconnects and Future Perspectives


Dr. Paul S. Ho is the Director of the Laboratory for Interconnect and Packaging at The University of Texas at Austin. He received his B.S. degree in mechanical engineering from National Chengkung University, Taiwan; M.S. degree in physics from National Tsinghua University, Taiwan; and Ph.D. degree in physics from Rensselaer Polytechnic Institute. He joined the Materials Science and Engineering Department at Cornell University in 1966 and became an Associate Professor in 1972. In 1972, he joined the IBM T.J. Watson Research Center and has held a number of management positions. In 1985, he became Senior Manager of the Interface Science Department. In 1991, he joined the faculty at The University of Texas at Austin and was appointed the Cockrell Family Regents Chair in Materials Science and Engineering. His current research is in the areas of materials and processing science for interconnect and packaging for microelectronics. He received the Outstanding Alumni Achievement Award from National Chengkung University in 1992, the Michel Lerme Award from the International Interconnect Technology Conference in 1999 and the Thomas D. Callinan Award from the Electrochemical Society in 2001. He holds the inventorship of 15 U.S. Patents in microelectronics technology. He has edited six books and published extensively in the area of thin films and materials science for microelectronics. He is a Fellow of the American Physical Society, the American Vacuum Society and IEEE.



Dr. Ajith Amerasekera, University of California, Berkeley

Reliability and Robustness in the Fully Connected World


Dr. Ajith Amerasekera is the Executive Director of the UC Berkeley Wireless Research Center (BWRC) at the University of California, Berkeley, an IEEE Fellow and former Texas Instruments Fellow. Ajith received his PhD in 1986 from Loughborough University, England, and joined Philips Research Labs, Eindhoven, the Netherlands, where he worked on the first submicron CMOS technology.  In 1991, he joined Texas Instruments, Dallas, and over 25 years made technical contributions ranging from transistors to circuits and systems. In 2008, he was the founding director of TI’s Kilby Research Labs where he was responsible for creating the research processes to address long-term exploration and innovation for new markets and technologies. Ajith became CTO for the High Performance Analog Division at Texas Instruments in 2012, responsible for strategic technology and business development. His innovations have been in use in many of TI’s industry leadership products from DSPs to wireless chipsets to network routing ASICs for over two decades. He joined UC Berkeley in 2016, and his research interests are in ubiquitous connected systems leveraging electronics in new application areas. Ajith has been an IEEE Distinguished Lecturer for the Solid State Circuits Society, and has over 150 papers and presentations as well as 4 books on integrated circuits.  He has been on the technical program committees of numerous IEEE symposia including the IEDM, ISSCC, and the VLSI Symposium.


Confirmed Speakers and Titles:


Prof. William D. Nix, Stanford University, USA

Growth and characterization of single-crystalline and bi-crystalline thin films for reliability studies


Prof. Dr. Ehrenfried Zschech, Fraunhofer IKTS, Dresden, Germany

3D visualization of reliability-limiting defects and processes in advanced packaging and BEoL stacks using X-ray microscopy


Prof. Reinhold H. Dauskardt, Stanford University, USA

Exploiting Extreme Molecular-Confinement in Dielectric Hybrids for Enhanced Mechanical and Thermal Behavior


Prof. Hai-Bao Chen, Shanghai Jiao Tong University, China

Physics-Based Analytical Modeling of Electromigration Reliability for Multi-Segment Interconnect Wires


Prof. Sheldon X. Tan, UC Riverside, USA

Fast EM-Aging Acceleration Techniques for VLSI Interconnects


Prof. Farid N. Najm, University of Toronto, Canada

Efficient Simulation of Electromigration Damage in Large Chip Power Grids


Dr. Norman Chang, ANSYS, USA

Applying Machine Learning to Design for Reliability


Prof. Dr. Alex Dommann, Empa, Swiss Federal Laboratories for Materials Science and Technology, Switzerland

MEMS reliability analysis using X-ray techniques


Prof. Jens Lienig, TU Dresden, Germany

The Pressing Need for Electromigration-Aware IC Physical Design


Prof. I. Cevdet Noyan, Columbia University, USA

Average and local strain fields in nanocrystals


Dr. Xiaopeng Xu, Synopsys, USA

Multiscale stress evolution and FinFET thermal analysis in advanced packages


Prof. Hiu-Yung Wong, San Jose State University, USA

SRAM Radiation Effect Study using DTCO Approach


Dr. Christine Hau-Riege, Qualcomm, USA

Electromigration Studies in Far Backend Interconnects


Dr. Jin-Woo Han, NASA Ames, USA

Sustainable Reliability on Silicon Devices


Prof. Debbie G. Senesky, Stanford University, USA

Extreme Harsh Environment Operation of Gallium Nitride Microelectronics


Prof. Dr. Hajdin Ceric, TU Vienna, Austria

Assessment of Electromigration in Nano-Interconnects


Prof. Sachin Sapatnekar, University of Minnesota, USA

Analyzing on-chip electromigration: From wires to systems


Prof. Carl V. Thompson, MIT

Stress and Structure Evolution in Electrodes for Thin Film Li-ion Batteries


Prof.  Kirsten Weide-Zaage, Leibniz Universität Hannover, Germany


Harsh environmental stress effects on metallization and solder


Dr. Hideya Matsuyama, Socionext Inc., Japan

Verification of Copper stress migration under low temperature long time stress and consideration the picture for its mechanism


Prof. Arief Budiman, SUTD, Singapore

Interfacial Sliding in Nanoscale Cu/Nb Multilayers – Enabling Extreme Materials Design and Novel Functionalities for Next Generation Stretchable/Wearable Devices


Prof. Francesca Iacopi, University of Technology Sydney, Australia

Wafer–level epitaxial graphene on cubic SiC on silicon: applications and reliability aspects


Dr. Stephane Moreau, CEA Leti, France

Correlation between Electromigration-Related Voids Volumes and Times-to-Failure by High Resolution X-Ray Tomography


Prof. Olivier Thomas, Aix-Marseille Université, France

Advanced in-situ synchrotron X-ray diffraction experiments for the evaluation of strains and defects in functional materials


Dr. Jiwoong Sue, SK Hynix, Korea

Effect of scaling and mechanical stress on feature level structure of memory device



Self heating reliability considerations in advanced RF SOI technology


Dr. Armen Kteyan, Mentor, a Siemens Business, Armenia

Finite element modeling the synergy between stress-induced and electromigration-induced voids and its evolution in interconnects


Dr. Jun-Ho Choy, Mentor, a Siemens Business, USA

Assessment of thermal-mechanical impact on IC reliability and performance


Prof. James Lloyd, SUNY Polytechnic Institute, USA

Stress relaxation in pulsed power DC electromigration

Mr. Gavin D.R. Hall, ON Semiconductor, USA

Probabilistic Compact Modeling for BEOL Reliability Failure Modes


Prof. Ellen Hieckmann, TU Dresden, Germany

Investigations of internal stresses in high-voltage devices with deep trenches


Dr. Chao-Kun (CK) Hu, IBM, USA
Electromigration and resistivity in Cu, Ru and Co damascene nano-interconnects


Prof. Paul Franzon, North Carolina State University, Raleigh, USA

Stress Modeling for Heterogeneous Integration


Prof. Chris Kim, University of Minnesota

Circuit based Characterization of Power Grid and Interconnect Electromigration Effects


Prof. Mehdi Tahoori, Karlsruhe Institute of Technology, Karlsruhe, Germany

Cross-Layer Approaches for Resilient VLSI System Design




This list will be updated upon receiving new confirmations.